Date of Award

1-1989

Document Type

Thesis

Degree Name

Master of Science (MS)

Department

Electrical Engineering and Computer Science

First Advisor

R. G. Deshmukh

Second Advisor

B. G. Grossman

Third Advisor

D. R. Clutterham

Fourth Advisor

J. Hadjilogiou

Abstract

The objective of this thesis is to investigate various multiprocessor system structures and to implement and test the resultant system configuration that offers high reliability and availability, ease of expansion, ease of programming, and increased computing performances. The resultant system is a MC68000 based tightly coupled multiprocessor system with large local memories and local I/Os, arbitrated by a specially designed arbitration circuit to implement pseudo random global bus granting. Each of the computer modules is an enhanced independent uniprocessor system with channel access switches to access the global memory. In its multiprocessor mode one computer module cooperates with the other computer modules to solve a problem at an increased execution rate compared to an uniprocessor. The detailed design of the multiprocessor system and the system performance analysis results are discussed.

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