Date of Award

1991

Document Type

Dissertation

Degree Name

Doctor of Philosophy (PhD)

Department

Electrical Engineering and Computer Science

First Advisor

R. G. Deshmukh

Second Advisor

T. J. Sanders

Third Advisor

Mehdi M. Shahsavari

Fourth Advisor

N. Tepedelenlioglu

Abstract

A new dataflow concept, Multiple Input Node is introduced to overcome the performance and efficiency degradation problems that exist in the current dataflow computation models where the computation unit, node, accepts 2 tokens at a time. Multiple Input Node is a new computation node which has 4 inputs, hence it can accept up to 4 token packets at a time. It can perform any simple arithmetic operation or combination of operations on these 4 input tokens. It is represented by a single instruction and performs the operations in a single instruction execution. This unique Multiple Input Node architecture reduces the number of token packets in the system, thus increases the performance. This study also introduces a newly designed dataflow processor architecture, Multiple Input Node Dataflow Processor, which uses the Multiple Input Node concept. Beside its use of the Multiple Input Node concept, the other very important feature of this dataflow processor is that it eliminates the need for a matching unit and very costly matching process which is also identified as a major bottleneck for the dataflow computation models. The Multiple Input Node Dataflow Processor also has RISC based design, 4 stage pipeline architecture and a peak performance of 60 MIPS. The processor has been designed by CAD tools and the resulting design has shown that the processor executes faster and possesses fewer number of gates than the com patible dataflow processor architectures.

Comments

Copyright held by author

Download

Share

COinS