Date of Award
12-2023
Document Type
Thesis
Degree Name
Master of Science (MS)
Department
Electrical Engineering and Computer Science
First Advisor
Naveed Mahmud
Second Advisor
Siddhartha Bhattacharyya
Third Advisor
Carlos E. Otero
Fourth Advisor
Brian Lail
Abstract
High-performance reconfigurable computers (HPRCs) make use of Field-Programmable Gate Arrays (FPGAs) for efficient emulation of quantum algorithms. Generally, algorithm-specific architectures are implemented on the FPGAs and there is very little flexibility. Moreover, mapping a quantum algorithm onto its equivalent FPGA emulation architecture is challenging. In this work, we present an automation framework for converting quantum circuits to their equivalent FPGA emulation architectures. The framework processes quantum circuits represented in Quantum Assembly Language (QASM) and derives high-level descriptions of the hardware emulation architectures for High-Level Synthesis (HLS) on HPRCs. The framework generates the code for a heterogeneous architecture consisting of a microprocessor (host) and FPGA (kernel). Space-time tradeoffs were investigated for the different architectures. We also explored methods for concurrent kernel execution to improve the circuit execution time.
Recommended Citation
Maurya, Anshul, "QASM-to-HLS: A Framework for Accelerating Quantum Circuit Emulation on High-Performance Reconfigurable Computers" (2023). Theses and Dissertations. 1385.
https://repository.fit.edu/etd/1385
Included in
Computer and Systems Architecture Commons, Computer Sciences Commons, Hardware Systems Commons, Other Computer Engineering Commons, VLSI and Circuits, Embedded and Hardware Systems Commons
Comments
Copyright held by author